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The first 3G transceiver architecture that implements all 3G signal processing functions on an ingeniously designed multicore DSP. The multicore DSP achieves the power efficiency of ASIC-based solutions and yet takes up only a fraction of the silicon area. The processing capacity adequately covers the MIMO and dual-carrier HSPA, and can be scaled for future HSPA evolutions.

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第一个将全部3G数字信号处理功能实现在一枚巧妙设计的多核数字信号处理器上的3G收发器架构。多核数字信号处理器具有与基于ASCI的收发器相当的功耗，但尺寸只是后者的一小部分。多核数字信号处理器可以绰绰有余地处理MIMO和双载频HSPA，并可以很方便地扩充以适应未来HSPA的需求。